(Quartus II implementation) An RT level combinational sorter circuit with three 8-bit
inputs A, B, and C is to be designed. Data on these inputs is unsigned binary numbers.
The circuit has W, X, and Y eight-bit outputs. The outputs of the circuit should become
the input data on A, B, and C sorted in the descending order. This circuit is a
A. Show a block diagram of the sorter circuit using comparators, multiplexers, and other
gates or RTL components as needed.
B. Implement this circuit using schematic in Quartus II.
C. Test your design and verify functionality of the circuit.